Field of the Invention
The invention relates to an evaluation circuit for evaluating the electrical charge of a memory cell and to a memory device having such an evaluation circuit.
Dynamic random access memories (DRAMs) include a plurality of memory cells which each include a storage capacitor and a selection transistor. These memory cells are addressed via word and bit lines which are provided as columns and rows. A memory cell is written to by charging the associated storage capacitor of the memory cell with an electrical charge corresponding to the respective binary data unit.
During a read-out operation, the stored charge is then read out and amplified by an evaluation circuit connected to the bit line of the memory cell and the electrical potential of the bit line is compared with the electrical potential of an associated reference line. Depending on the potential difference, the two electrical potentials are amplified to two predetermined potential values, the higher potential of the two lines generally being pulled to the potential of the supply voltage and the lower potential being pulled to the ground potential.
The storage capacitor loses its charge over time due to leakage currents within the memory cell. For this reason, the charge of a memory cell must continually be refreshed again by reading and rewriting at short time intervals.
The signals in large scale integrated memory cell configurations are exposed to numerous interference sources in particular within the bit lines which connect the memory cells to the evaluation circuits. In this case, primarily a coupling capacitance between bit lines running parallel to one another occurs as an interference factor. The electrical potential of a bit line is influenced by the electrical potentials of adjacent bit lines. The temporal fluctuation of this parasitic coupling signal causes a noise which is referred to as coupling noise and, on account of superposition with the actual signal, has an interfering effect during the read-out of the memory cell.
The decreasing distancesxe2x80x94as a result of miniaturizationxe2x80x94between adjacent bit lines of a large scale integrated memory cell configuration mean that the coupling capacitance between the bit lines rises, so that it often exceeds the capacitance of the memory cells by a multiple in the case of today""s memory configurations. The coupling noise then reaches the order of magnitude of the actual signals, so that, in an unfavorable case, the actual charge state of the storage capacitor may be misinterpreted by the evaluation circuit.
In order to increase the reliability of such memory devices, it is therefore primarily attempted to reduce the coupling capacitances of the bit lines between the evaluation circuits and the memory cells. A bit line with reduced coupling capacitance has a more favorable signal-to-noise ratio, which is in turn manifested in the reduction of the error rate in the interpretation of the memory cell information.
The continuous trend toward ever higher storage densities necessitates further measures, however. In particular, it is found that further, hitherto largely unknown interference factors also play a part in the error rate of the information evaluation of the memory cells.
It is accordingly an object of the invention to provide a memory device which overcomes the above-mentioned disadvantages of the heretofore-known memory devices of this general type and which reduces the coupling capacitances of the signal lines within a memory cell configuration and which has a minimal error rate in the evaluation of the memory cell information.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory device, including:
a memory cell;
an evaluation circuit;
a reference line connected to the evaluation circuit
a bit line defining a bit line direction;
the memory cell being connected to the evaluation circuit via the bit line;
a first signal line, the bit line being connected, within the evaluation circuit, to the first signal line;
a second signal line, the reference line being connected, within the evaluation circuit, to the second signal line;
the bit line and the reference line having respective electrical potentials, the evaluation circuit amplifying a difference between the respective electrical potentials of the bit line and the reference line; and
the first and second signal lines having a crossover region within the evaluation circuit, the crossover region forming sections along the bit line direction in the evaluation circuit, the sections along the bit line direction having mutually substantially corresponding capacitances.
In other words, a memory device having a memory cell and an evaluation circuit is provided, the memory cell being connected to the evaluation circuit via a bit line, and a reference line being connected to the evaluation circuit, within the evaluation circuit the bit line being connected to a first signal line and the reference line being connected to a second signal line, and the evaluation circuit amplifying the difference between the electrical potentials of the bit line and the reference line, wherein the first and second signal lines have, within the evaluation circuit, a crossover region, the capacitances of the sections of the evaluation circuit which are formed by the crossover region in the bit line direction essentially mutually correspond to one another.
According to another feature of the invention, the first and second signal lines extend through the evaluation circuit; the evaluation circuit has two sides, the bit line and the reference line make contact with a respective one of the first signal line and the second signal line at the two sides of the evaluation circuit; and the bit line is connected to the memory cell on a first one of the two sides of the evaluation circuit and is connected to a further memory cell on a second one of the two sides of the evaluation circuit.
According to yet another feature of the invention, the evaluation circuit has a high-resistance input region for each of the bit line and the reference line.
According to another feature of the invention, the evaluation circuit is a measurement amplifier or a sense amplifier; and the amplifier amplifies the respective electrical potentials of the bit line and of the reference line in accordance with the difference between the respective electrical potentials such that the respective electrical potentials are amplified to two given potential values.
According to a further feature of the invention, the reference line is configured as a bit line for a further memory cell.
According to another feature of the invention, the memory cell is a dynamic random access memory cell.
According to yet another feature of the invention, the sections formed by the crossover region along the bit line direction have capacitances that substantially compensate one another.
According to another feature of the invention, a plurality of evaluation circuits is disposed as a matrix configuration; a plurality of memory cells is disposed between two evaluation circuits along the bit line; and the evaluation circuits are configured such that, in the word line direction, respective ones of the first and second signal lines form respective crossover regions in every other one of the evaluation circuits.
It has been found that, in particular, the parallel signal lines within an evaluation circuit which are connected to a bit line and an associated reference line also have interfering coupling capacitances. In this case, the resultant coupling noise can likewise lead to misinterpretations of the charge state of the associated storage capacitor and thus to read errors.
According to the invention, therefore, the first and second signal lines have, within the evaluation circuit, at least one crossover region which subdivides the evaluation circuit along the bit line direction into at least two sections whose coupling capacitances mutually compensate for one another. The signal lines of the evaluation circuit preferably have exactly one crossover region which is arranged exactly in the capacitive mid point of the evaluation circuit, so that, on account of the position change of the signal lines of the two sections, the potential difference coupled from an adjacent line into one of the two sections has the same magnitude but an opposite sign. This makes it possible to minimize the coupling noise within the evaluation circuit.
In a further advantageous embodiment of the invention, the input regions of the evaluation circuit for the bit line and the reference line are high-impedance input regions. As a result, the evaluation circuit does not xe2x80x9cperceivexe2x80x9d the coupling noise outside the evaluation circuit, i.e. on the bit line and the reference line, and can therefore be regarded practically as decoupled from the lines for the short time period of the evaluation. Consequently, the parasitic coupling capacitance can be largely compensated solely by the crossover region of the lines within the evaluation circuit in accordance with the invention. In addition to the reduction of the error rate, the speed of the evaluation operation can thus also be increased again, which benefits the access speed in the memory.
In a further advantageous embodiment of the invention, the evaluation circuits are arranged in rows and columns. Since the capacitance of two lines behaves reciprocally with respect to the distance between the lines, the coupling capacitances of the signal lines of two evaluation circuits that are not directly adjacent make a significantly smaller contribution to the coupling noise than the directly adjacent signal lines. Therefore, it generally suffices to form, in accordance with the invention, the crossover of the signal lines in every second evaluation circuit along the word line.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an evaluation circuit for a DRAM, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.